1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and, more particularly, to a technique of planarizing a surface of a semiconductor film.
2. Description of the Related Art
Thin film transistors (hereinafter referred to as “TFTs”) are manufactured in a related art as follows.
FIG. 1 illustrates the state of a surface of a polycrystallized silicon film, and FIGS. 2A-2D are cross sectional views illustrating steps of manufacturing a thin film transistor according to the related art taken along the line A—A in FIG. 1.
Step 1 (FIG. 2A): On an insulating substrate 10 formed of glass, quartz glass, or the like, an insulating film 11 of SiN and/or SiO2 is formed through a CVD method. An amorphous silicon film (hereinafter referred to as an “a-Si film”) 12 is formed on the film 11 through the CVD method.
Step 2 (FIG. 2B): The a-Si film 12 is irradiated with a XeCl, KrF, ArF, or similar linear excimer laser beam (beam of focused laser light) 14 scanning the film 12 from one end to the other for annealing, thereby melting and recrystallizing the a-Si film 12 for polycrystallization. As a result, a polycrystallized silicon film (hereinafter referred to as a “p-Si film”) 313 is obtained.
During the above step, the surface of the a-Si film 12 is irradiated with the excimer laser beam 14 scanning in the direction of the arrow (leftward in the figure), thereby melting and recrystallizing the a-Si film 12. More specifically, the a-Si film 12 heated by irradiation of the laser beam 14 is allowed to cool and recrystallized, resulting in a p-Si film 313.
Step 3 (FIG. 2C): On the p-Si film 313, a gate insulating film 14 is formed of an SiO2 film over the entire surface through a CVD method. A film of a refractory metal, such as chromium (Cr) and molybdenum (Mo), is formed by sputtering, and patterned to a predetermined shape through dry etching using photolithography and RIE (reactive ion etching) techniques, thereby producing a gate electrode 15.
When a P-channel TFT is formed, P-type ions, such as boron (B), are doped to the p-Si film 313 through the gate insulating film 14 using the gate electrode 15 as a mask. For an N-channel TFT, N-type ions, such as phosphorous (P), are doped. Consequently, the portion of the active layer, i.e. the p-Si film 313, covered with the gate electrode 15 serves as a channel region 313c, and the portions located on both sides thereof serve as a source region 313s and a drain region 313d. 
Next, an interlayer insulating film 16 composed of a single SiO2 film or two layers of SiO2 film and SiN film is formed through the CVD method.
Step 4 (FIG. 2D): A first contact hole 17 penetrating the interlayer insulating film 16 and the gate insulating film 14 is formed at a position corresponding to the drain region 313d to reach the p-Si film 313, and a drain electrode 19 of a metal, such as aluminum, is formed in the first contact hole 17 portion. The drain electrode 19 is formed by, for example, depositing aluminum on the interlayer insulating film 16 having the thus-formed first contact hole 17 through sputtering, and patterning aluminum filled in the first contact hole 17.
For application in display devices, a planarization insulating film 20 is then provided on the interlayer insulating film 16 and the drain electrode 19 to planarize the surface. The planarization insulating film 20 formed by applying and baking a solution of an acrylic resin fills in concave portions produced by the gate electrode 15 and the drain electrode 19, contributing to surface planarization.
On the source region 313s, a second contact hole 21 penetrating the planarization insulating film 20, the interlayer insulating film 16, and the gate insulating film 14 is further formed. A display electrode 22 connected to the source 313s and spreading over the acrylic resin layer is formed in the portion where the second contact hole 21 is formed. The display electrode 22 is obtained by providing a transparent conductive film, such as an ITO (indium tin oxide) film, on the planarization insulating film 20 having the second contact hole 21 formed therein, applying a resist film on the transparent conductive film, processing the film to a predetermined electrode pattern, and etching the exposed transparent conductive film by a dry etching method, such as RIE, using HBr gas and Cl2 as an etching gas.
However, in the TFT manufactured through polycrystallization according to the above-described manufacturing method of the related art, grain boundaries of crystals collide with one another when the a-Si film is melted and recrystallized by laser beam irradiation, and the a section where there is such a collision may rise to form a projection 300. As a result, the thickness of the gate insulating film 14 is reduced at a portion located on the projection 300 of the p-Si film 13. When the p-Si film 313 has a thickness of, for example, approximately 40 nm, the projection 300 also has a thick of approximately 40 nm. As a result, sufficient insulation between the p-Si film 313 and the gate electrode 15 cannot be ensured, or a short circuit is formed between the p-Si film 313 and the gate electrode 15 when the height of the projection 300 exceeds the thickness of the gate insulating film 14.
Further, an electric field is focused to the projection 300 by an applied voltage, thereby causing dielectric breakdown and, therefore, short-circuiting the p-Si film 313 and the gate electrode 15.
Still further, the voltage of the gate electrode 15 applied to the p-Si film 313 varies along the surface of the insulating substrate surface, producing TFTs with nonuniform characteristics. When such TFTs are used in a display device, such as a liquid crystal display device, there may be visible inconsistencies in the displayed images.